1. Field of the Invention
The present invention relates to an output driver circuit such as an output buffer circuit in semiconductor integrated circuits. More particularly, the invention relates to an output buffer circuit for use in an integrated circuit operating on a supply voltage lower than those of other integrated circuits connected to the output bus within a system that mixedly comprises semiconductor integrated circuits operating on different supply voltages.
2. Description of the Related Art
Transistors in semiconductor integrated circuits have been progressively reduced in size in keeping with the growing degree of circuit integration. In the face of this trend, it is preferred to lower the supply voltage to the integrated circuit so as to minimize any deterioration in the reliability of transistors therein caused by the so-called hot electron effect. As the supply voltage is lowered, so are the power consumption and the circuit switching speed of the integrated circuit involved.
MOS integrated circuits used to operate on a supply voltage of 5 V. Today, many of the MOS devices are designed to run on the supply voltage of as low as 3.3 V.
Reductions in the supply voltage not only minimize the hot electron effect on transistors; they also lower power dissipation per transistor in the integrated circuit. This means that, where numerous transistors are integrated on a single chip, the power consumption per unit area of the chip may be reduced appreciably. This is an important factor affecting the scale of integration and the operating speed of the integrated circuit.
Meanwhile, where a system is configured using a plurality of semiconductor integrated circuits, some of the configured circuits may operate on different supply voltages because the transistor-transistor logic (TTL) runs on the 5-volt power supply. In that case, it is customary for those circuits operating on the different supply voltages to connect with a common bus in the system.
FIG. 17 is a schematic block diagram of a conventional system wherein semiconductor integrated circuits operate on different supply voltages (this is a first conventional example). In FIG. 17, integrated circuits 7 and 107 operate on different supply voltages and are connected to a common bus 1000.
The integrated circuit 7 operates on a first supply voltage of, say, 3.3 V. An output buffer circuit 5 in the integrated circuit 7 is controlled by internal signals D and HZ. The output buffer circuit 5 outputs its signal to an output node 3. The internal signal D is a data signal that represents a first and a second logical level output to the output node 3. The internal signal HZ is a signal that puts the output node 3 in the high-impedance state.
The output buffer circuit 5 comprises a control circuit 6, a p-channel MOS transistor 1 and an n-channel MOS transistor 2. The back gates of these transistors are connected to their respective sources. The common drain of these transistors is connected to the output node 3. The source of the n-channel MOS transistor 2 is connected to ground, while the source of the p-channel MOS transistor 1 is connected to a power line 4.
The control circuit 6 comprises a NAND gate 601, a NOR gate 602 and an inverter 603. The internal signal D is input to a first input of the NAND gate 602 and to a first input of the NOR gate 602. The internal signal HZ is input to a second input of the NAND gate 601 via the inverter 603 and a second input of the NOR gate 602. The output signal DP of the NAND gate 601 is input to the gate of the p-channel MOS transistor 1. The output signal DN of the NOR gate 602 is input to the gate of the n-channel MOS transistor 2.
The integrated circuit 107 is suitably constituted to operate on a second supply voltage of, say, 5 V. An output buffer circuit 105 in the integrated circuit 107 is the same in constitution as the output buffer circuit 5 in the integrated circuit 7, except that the circuit 105 operates on the supply voltage of 5 V. Thus the output buffer circuit 105 will not be discussed further. As with the integrated circuit 7, the output node 103 of the output buffer circuit 105 is connected to the bus 1000.
Below is a description of how the output buffer circuit 5 operates in response to the internal signals D and HZ. The basic operation of the output buffer circuit 5 is dependent on the logical values of the data signal D and impedance control signal HZ. That is, the output buffer circuit 5 selectively performs one of three functions at any one time: to bring the output node 3 high, to drive the output node 3 low, or to put the output node in the high-impedance state.
The control circuit 6 operates as follows: when the impedance control signal HZ is low, the control circuit 6 outputs the inverted logical values DP and DN of the data signal D. Specifically, if the data signal D is high, the output signals DP and DN are low; if the data signal D is low, the output signals DP and DN are high.
When the impedance control signal HZ is at the high level, the output signal DP is unconditionally high and the output signal DN is unconditionally low regardless of the logical value of the data signal D.
In response to the way the control circuit 6 operates, the output buffer circuit 5 operates as described below. First to be noted is how the p-channel MOS transistor 1 and the n-channel MOS transistor 2 operate when the impedance control signal HZ is low. If the data signal D is high, the p-channel MOS transistor 1 is turned on and the n-channel MOS transistor 2 is turned off. This gets a signal S3 of the output node 3 ready to go high. If the data signal D is low, the p-channel MOS transistor 1 is turned off and the n-channel MOS transistor 2 is turned off. This in turn gets the signal S3 of the output node 3 ready to go low.
In the above situation, if the output node 103 of the integrated circuit 107 is in the high-impedance state, the output of the output buffer circuit 5 is given priority. That is, the logical value BUS of the bus 1000 becomes the same as that of the signal S3.
If the impedance control signal HZ is at the high level, both the p-channel MOS transistor 1 and the n-channel MOS transistor 2 are turned off. This puts the output node 3 of the output buffer circuit 5 in the high-impedance state, disconnecting the circuit 5 electrically from the bus 1000. In that case, the logical value S103 of the output node 103 of the other integrated circuit 107 is given priority.
The above-described operation of the output buffer circuit 5 is summarized in the truth table of FIG. 18. Reference characters 1, 0 and Z represent the high level state, the low level state and the high-impedance state, respectively. Reference characters S103, S3 and BUS stand for the logical value of output 103 from other integrated circuit 107, the logical value of output node 3 and the logical value of bus line 1000, respectively. Reference characters Tr1 and Tr2 represent the on/off state of the transistor 1 and that of the transistor 2, respectively. FIG. 19 is a crosssectional view of the p-channel MOS transistor 1 and the n-channel MOS transistor 2 in the output buffer 5. Reference characters G, S, D and B stand for the gate, source, drain and back gate, respectively, of each of the transistors. Reference characters p and n represent a p-type and an n-type semiconductor region, respectively.
The integrated circuit 107 operates on a supply voltage higher than that of the integrated circuit 7. When the circuit 107 is disconnected electrically from the bus 1000, i.e., when the output node 3 of the integrated circuit 7 outputs a high-level or a low-level signal, the circuit of FIG. 19 works normally.
On the other hand, with the output buffer circuit 5 in the high-impedance state (i.e., signal HZ driven high), it may happen that the integrated circuit 107 outputs a high-level signal while the supply voltage of the circuit 107 remains higher than that of the output buffer circuit 5. In that case, an irregularity occurs.
That is, in FIG. 19, the potential of the output node 3 becomes higher than that of the power line 4 of the output buffer circuit 5. This turns on the p-channel MOS transistor 1. Furthermore, the p-n junction between the drain and the n-well in the p-channel MOS transistor 1 is forward-biased because the potential of that drain is higher than that of the back gate. As a result of this, a current flows from the output node 3 to the power line 4.
More specifically, what happens is as follows: in FIG. 17, a large leak current flows from the power supply of the other integrated circuit 107 to the power line 4 of the output buffer circuit 5 through the output node 103 of the integrated circuit 107, the bus 1000, the output node of the integrated circuit 7, and the drain and back gate of the p-channel MOS transistor 1 in the output buffer circuit 5.
The leak current in turn can lead to an abnormal increase in the power consumption of the integrated circuit 107 and also result in fused or severed wiring in the current transmission path.
One solution to the above problem is disclosed in U.S. Pat. No. 5,151,619 (a second conventional example). FIG. 20 is a schematic block diagram of the disclosed circuit constitution. In FIG. 20, a rectangle having a diagonal line inside and a gate electrode nearby indicates a p-channel MOS transistor; a rectangle with a gate electrode nearby represents an n-channel MOS transistor.
In this output buffer circuit, the basic component is made of a pull-up p-channel MOS transistor 212 and a pull-down n-channel MOS transistor 214 connected in series. The source of the p-channel MOS transistor 212 is fed with a supply voltage V.sub.dd. The source of the n-channel MOS transistor 214 is connected to ground. The common drain of the two transistors is connected to an output node V.sub.out.
A pre-driver circuit 210 corresponds to the control circuit 6 in the first conventional example. When signal IN and IN' turn on and off the p-channel MOS transistor 212 and n-channel MOS transistor 214 in a complementary manner, a first and a second logical levels are output to the output node V.sub.out. When the two transistors are simultaneously turned off, the output node V.sub.out is put in the high-impedance state.
The second conventional example differs from the first example in three major aspects. One difference is that a p-channel MOS transistor 216 whose gate is fed with a reference potential V.sub.c is connected interposingly between the output node V.sub.out and the gate electrode of the p-channel MOS transistor 212.
Another difference is that an n-well is connected to the supply potential V.sub.dd by way of a p-channel MOS transistor 218. The source, drain and gate of the p-channel MOS transistor 218 are connected to the supply potential V.sub.dd, n-well 220 and output node V.sub.out, respectively.
A further difference is that the output IN of the pre-driver circuit (corresponding to the control circuit 6 in FIG. 17) is connected to the gate of the p-channel MOS transistor 212 via a transmission gate 222. The transmission gate 222 is structured as follows:
The transmission gate 222 includes an n-channel MOS transistor 224 connected interposingly between the output IN of the pre-driver circuit and the gate of the p-channel MOS transistor 212. The gate of the n-channel MOS transistor 224 is biased to the supply potential. The transmission gate 222 also includes a p-channel MOS transistor 226 connected parallelly to the n-channel MOS transistor 224. The gate of the p-channel MOS transistor 226 is connected to the output node V.sub.out.
FIG. 21 is a cross-sectional view of the transistors constituting the circuit of FIG. 20. How the second conventional example operates will now be described with reference to FIGS. 20 and 21. It is assumed hereunder that the reference potential V.sub.c is equal to the supply potential V.sub.dd. It is also assumed that the supply potential V.sub.dd is 3.6 V and that the output node V.sub.out is supplied with 0 V or 5.5 V from a second circuit 228 through a switch 230 which is opened and closed.
When the gate potential of the p-channel MOS transistor 212 is high (3.6 V) and the gate potential of the n-channel MOS transistor 214 is low (0 V), the output of the circuit in FIG. 20 is in the high-impedance state. In that state, closing the switch 230 feeds the voltage of 0 V or 5.5 V from the external circuit 228 to the output node V.sub.out.
When the voltage fed to the output node V.sub.out is raised to a threshold voltage higher than the voltage V.sub.c (=V.sub.dd), the p-channel MOS transistor 216 is turned on. This raises the gate potential of the p-channel MOS transistor 212 up to the potential of the output node V.sub.out.
Because the source/n-well junction of the p-channel MOS transistor 216 is forward-biased, a current flows through the n-well 220. This raises the potential of the n-well 220, which is electrically floating, to the level of the voltage of the output node V.sub.out minus the threshold voltage of the p-n junction.
Because the p-channel MOS transistor 212 is located in the n-well 220, a positive voltage develops between the gate electrode and the source. This allows the p-channel MOS transistor 212 to remain off, preventing the current to flow toward the power supply V.sub.dd.
With the gate potential of the p-channel MOS transistor 212 raised, the n-channel MOS transistor 224 is turned off as well. This prevents any current from flowing to the pre-driver circuit 210. Needless to say, the p-channel MOS transistor 226 is also off at this point.
If the p-channel MOS transistor 226 is absent from the transmission gate 222 which then would consist of the n-channel MOS transistor 224 alone, the potential of the signal IN will be lowered by the amount equivalent to the threshold voltage of the absent transistor. A full-swing signal is fed to the gate of the pull-up transistor 212 only when the transmission gate 222 is furnished with the n-channel MOS transistor 224 whose gate is biased to the potential V.sub.dd as well as the p-channel MOS transistor 226 whose gate is biased to the output node V.sub.out.
With all their improvements, the first and the second conventional example outlined above still have three major disadvantages between them.
The first conventional example has two disadvantages. One is that with the output node 3 of the output buffer circuit 5 placed in the high-impedance state, the p-channel MOS transistor 1 is turned on when the output node voltage becomes higher than the supply voltage of the circuit 5. This makes it impossible to maintain the high-impedance state.
The other disadvantage of the first conventional example is that with the high-impedance state removed, the p-n junction between the drain and the n-well of the p-channel MOS transistor 1 is forward-biased. The path thus formed also lets a leak current flows therethrough.
The major disadvantage of the second conventional example is that the measures taken to overcome the above two problems make the circuit constitution complicated. This leads to a growing number of transistors in, and a wider layout area of, the output buffer circuits required.